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Espressif Systems /ESP32-H2 /PCR /TIMERGROUP0_CONF

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Interpret as TIMERGROUP0_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TG0_CLK_EN)TG0_CLK_EN 0 (TG0_RST_EN)TG0_RST_EN 0 (TG0_WDT_READY)TG0_WDT_READY 0 (TG0_TIMER0_READY)TG0_TIMER0_READY 0 (TG0_TIMER1_READY)TG0_TIMER1_READY

Description

TIMERGROUP0 configuration register

Fields

TG0_CLK_EN

Set 1 to enable timer_group0 apb clock
TG0_RST_EN

Set 0 to reset timer_group0 module
TG0_WDT_READY

Query this field after reset timer_group0 wdt module
TG0_TIMER0_READY

Query this field after reset timer_group0 timer0 module
TG0_TIMER1_READY

reserved

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd